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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 16mx72 registered ddr sdram registered for enhanced performance of bus speeds of 200, 225, and 250 mhz package: ? 219 plastic ball grid array (pbga), 32 x 25mm 2.5v 0.2v core power supply 2.5v i/o (sstl_2 compatible) differential clock inputs (ck and ck#) commands entered on each positive ck edge internal pipelined double-data-rate (ddr) architecture; two data accesses per clock cycle programmable burst length: 2,4 or 8 bidirectional data strobe (dqs) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) dqs edge-aligned with data for reads; center- aligned with data for writes dll to align dq and dqs transitions with ck four internal banks for concurrent operation two data mask (dm) pins for masking write data programmable i ol /i oh option auto precharge option features 25 32 66 tsop 66 tsop 66 tsop 66 tsop 66 tsop 11.9 11.9 11.9 22.3 monolithic solution actual size s a v i n g s area i/o count 5 x 265mm 2 + 2 x 105mm 2 = 1536mm 2 5 x 66 pins + 2 x 48 = 426 pins 800mm 2 47% 219 balls 49% w3e16m72sr-xbx white electronic designs 48 tsop 12.6 48 tsop 12.6 8.3 11.9 22.3 22.3 auto refresh and self refresh modes commercial, industrial and military temperature ranges organized as 16m x 72 weight: w3e16m72sr-xbx - 2.5 grams typical benefits 47% space savings glueless connection to pci bridge/memory controller reduced part count reduced i/o count ? 49% i/o reduction reduced trace lengths for lower parasitic capacitance suitable for hi-reliability applications laminate interposer for optimum tce match upgradeable to 32m x 72 density (contact factory for information) * this product is subject to change without notice.
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 figure 1 C pin configuration note: dnu = do not use; to be left unconnected for future upgrades. pin d8 will be a13, d9 will be a14, and d10 will be a15 a s needed. nc = not connected internally. top view 1 2345678910111213141516 a b c d e f g h j k l m n p r t dq1 dq3 dq6 dq7 cas# cs# v ss v ss ck3# nc dq56 dq57 dq60 dq62 v ss vss dq30 dq28 dq25 dq24 ck1 nc v cc v cc nc rv ref dq39 dq38 dq35 dq33 v cc dq0 dq2 dq4 dq5 dm0 we# ras# v ss v ss nc ck3 dm7 dq58 dq59 dq61 dq63 dq31 dq29 dq27 dq26 nc dm3 ck1# v ccq v ccq nc reset# dm4 dq37 dq36 dq34 dq32 dq14 dq12 dq10 dq8 v cc v cc v cc v cc v cc v cc v cc v cc dq55 dq53 dq51 dq49 dq17 dq19 dq21 dq23 v ss v ss v ss v ss v ss v ss v ss v ss dq40 dq42 dq44 dq46 dq15 dq13 dq11 dq9 dm1 ck0 cke v ccq v ccq nc nc nc dq54 dq52 dq50 dq48 dq16 dq18 dq20 dq22 dm2 rck0b rck1b v ss v ss nc ck2 dm5 dq41 dq43 dq45 dq47 v ss v ss v cc v ccq dqs7 dqs6 ck0# v ss v ss dqs8 nc dm6 dqs9 v ss v cc v ccq v ccq v cc v ss v ss v ref rck0 rck1 v cc v cc ck2# dqs4 nc dqs5 v cc v ss v ss a9 a0 a2 a12 dqs1 dm9 dq73 dq75 dq77 dq79 a8 a1 a3 dnu dqs2 nc dq70 dq68 dq66 dq64 a10 a7 a5 dnu ba0 ck4 dq72 dq74 dq76 dq78 a11 a6 a4 dnu ba1 nc dq71 dq69 dq67 dq65 v ss v ss v cc v ccq dqs0 nc ck4# v ss v cc v ccq v ccq v cc v ss v ss dqs3 nc dm8 v cc v ss v ss
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 v ref reset# a 0-12 ba 0-1 ck 0 #ck# cas# dq 0 dq 15 cke b cke dm 0 dqml dm 1 dqmh dq 0 dq 15 u1 a 0-12 ba 0-1 ck 1 #ck# dq 16 dq 31 ras b # we b # cas b # dq 0 dq 15 we# u0 ras# cke b cke dm 2 dqml dm 3 dqmh dq 0 dq 15 u2 a 0-12 ba 0-1 ck 2 #ck# dq 32 dq 47 cke b cke dm 4 dqml dm 5 dqmh dq 0 dq 15 u3 a 0-12 ba 0-1 ck 3 #ck# dq 48 dq 63 cke b cke dqs 6 dqsl dqs 7 dqsh dq 0 dq 15 u4 a 0-12 ba 0-1 ck 4 #ck# dq 64 dq 79 cke b cke dqs 8 dqsl dqs 9 dqsh y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = y = ck 4 ck v ref ck 3 ck v ref dqs 4 dqsl dqs 5 dqsh v ref dqs 2 dqsl dqs 3 dqsh v ref dqs 0 dqsl dqs 1 dqsh v ref ck 2 ck ck 1 ck ck 0 ck v ref dm 6 dqml dm 7 dqmh dm 8 dm 9 dqml dqmh u5 u6 cas b # ras b # we b # cs b # cke b # v ref reset# ras# cas# we# cs# cke rv ref reset# a 0-12 ba 0 - 1 sstv16857 sstv16857 rck 1 rck 1b rck 0 rck 0b cs b # cs# cas# we# ras# cs# cas# we# ras# cs# cas# we# ras# cs# cas# we# ras# cs# figure 2 C functional block diagram
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power- saving power-down mode. functional description read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register de? nition, command descriptions and device operation. initialization ddr sdrams must be powered up and initialized in a prede? ned manner. operational procedures other than those speci? ed may result in unde? ned operation. power must ? rst be applied to v cc and v ccq simultaneously, and then to v ref (and to the system v tt ). v tt must be applied after v ccq to avoid device latch-up, which may cause permanent damage to the device. v ref can be applied any time after v ccq but is expected to be nominally coincident with v tt . except for cke, inputs are not recognized as valid until after v ref is applied. cke is an sstl_2 input but will detect an lvcmos low level after v cc is applied. maintaining an lvcmos low level on cke during power- up is required to ensure that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200s delay prior to applying an executable command. general description the 128mbyte (1gb) ddr sdram is a high-speed cmos, dynamic random-access, memory using 5 chips containing 268,435,456 bits. each chip is internally con? gured as a quad-bank dram. each of the chips 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. the 128 mb ddr sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 128mb ddr sdram effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory contoller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. each chip has two data strobes, one for the lower byte and one for the upper byte. the 128mb ddr sdram operates from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self- timed row precharge that is initiated at the end of the burst access.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 once the 200s delay has been satis? ed, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a load mode register command should be issued for the extended mode register (ba1 low and ba0 high) to enable the dll, followed by another load mode register command to the mode register (ba0/ba1 both low) to reset the dll and to program the operating parameters. two-hundred clock cycles are required between the dll reset and any read command. a precharge all command should then be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed (t rfc must be satis? ed.) additionally, a load mode register command for the mode register with the reset dll bit deactivated (i.e., to program operating parameters without resetting the dll) is required. following these requirements, the ddr sdram is ready for normal operation. register definition mode register the mode register is used to de? ne the speci? c mode of operation of the ddr sdram. this de? nition includes the selection of a burst length, a burst type, a cas latency, and an operating mode, as shown in figure 3. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. (except for bit a8 which is self clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the speci? ed time before initiating the subsequent operation. violating either of these requirements will result in unspeci? ed operation. mode register bits a0-a2 specify the burst length, a3 speci? es the type of burst (sequential or interleaved), a4-a6 specify the cas latency, and a7-a12 specify the operating mode. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable, as shown in figure 3. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniq uely selected by a1- ai when the burst length is set to two; by a2-ai when the burst length is set to four (where ai is the most signi? cant column address for a given con? guration) ; and by a3-ai when the burst length is set to eight. the remaining (least signi? cant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 1. read latency the read latency is the delay, in clock cycles, between the registration of a read command and the availability of the ? rst bit of output data. the latency can be set to 2 or 2.5 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . table 2 below indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result.
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, output drive strength, and qfc#. these functions are controlled via the bits shown in figure 5. the extended mode register is programmed via the load mode register command to the mode register (with ba 0 = 1 and ba 1 = 0) and will retain the stored information until it is programmed again or the device loses power. the enabling of the dll should always be followed by a load mode register command to the mode register (ba 0 /ba 1 both low) to reset the dll. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the speci? ed time before initiating any subsequent operation. violating either of these requirements could result in unspeci? ed operation. figure 3 C mode register definition m3 = 0 2 4 8 reserved reserved reserved m3 = 1 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 00 valid valid 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a11 * m14 and m13 (ba0 and ba1 must be "0, 0" to select the base mode register (vs. the extended mode register). 0* 0* ba0 ba1 reserved reserved reserved reserved m9 m10 m11 0 0 0 10 0 0 0 -- - - - - a12 m12 0 0 - table 2 C cas latency speed allowable operating frequency (mhz) cas latency = 2 cas latency = 2.5 -200 75 100 -225 100 112.5 -250 100 125 operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a12 each set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. although not required, jedec speci? cations recommend when a load mode register command is issued to reset the dll, it should always be followed by a load mode register command to select normal operating mode. all other combinations of values for a7-a12 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. table 1 C burst definition burst length starting column address order of accesses within a burst type = sequential type = in ter leaved 2 a0 0 0-1 0-1 1 1-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 notes: 1. for a burst length of two, a 1 -ai select two-data-element block; a 0 selects the starting column within the block. 2. for a burst length of four, a 2 -ai select four-data-element block; a 0-1 select the starting column within the block. 3. for a burst length of eight, a 3 -ai select eight-data-element block; a 0-2 select the starting column within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 deselect the deselect function (cs# high) prevents new commands from being executed by the ddr sdram. the sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to the selected ddr sdram (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a 0-12 . the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. command read nop nop nop cl = 2.5 don't care transitioning data dq dqs t0 t1 t2 t2n t3 t3n command read nop nop nop cl = 2 dq dqs clk clk# t0 t1 t2 t2n t3 t3n burst length = 4 in the cases shown shown with nominal tac and nominal tdsdq data clk clk# output drive strength the normal full drive strength for all outputs are speci? ed to be sstl2, class ii. the ddr sdram supports an option for reduced drive. this option is intended for the support of the lighter load and/or point-to-point environments. the selection of the reduced drive strength will alter the dqs and dqss from sstl2, class ii drive strength to a reduced drive strength, which is approximately 54 percent of the sstl2, class ii drive strength. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. commands the truth table provides a quick reference of available commands. this is followed by a written description of each command. figure 4 C cas latency figure 5 C extended mode register definition dll enable disable dll ds a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 extended mode register (ex) address bus operating mode a 10 a 11 1 1 0 1 ba 0 ba 1 qfc# e0 0 1 drive strength normal reduced e1 0 1 qfc# function disabled reserved e2 2 0 - operating mode reserved reserved e2, e1, e0 valid - e12 0 - e10 0 - e9 0 - e8 0 - e7 0 - e6 0 - e5 0 - e4 0 - e3 0 - a 12 e11 0 - 1. e14 and e13 must be "0, 1" to select the extended mode register (vs. the base mode register) 2. the qfe# function is not supported.
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 notes: 1. cke is high for all commands shown except self refresh. 2. a 0-12 de? ne the op-code to be written to the selected mode register. ba 0 , ba 1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. a 0-12 provide row address, and ba 0 , ba 1 provide bank address. 4. a 0-8 provide column address; a 10 high enables the auto precharge feature (non persistent), while a 10 low disables the auto precharge feature; ba 0 , ba 1 provide bank address. 5. a 10 low: ba 0 , ba 1 determine the bank being precharged. a 10 high: all banks precharged and ba 0 , ba 1 are dont care. 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. applies only to read bursts with auto precharge disabled; this command is unde? ned (and should not be used) for read bursts with auto precharge enabled and for write bursts. 9. deselect and nop are functionally interchangeable. 10. used to mask write data; provided coincident with the corresponding data. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba 0 , ba 1 inputs selects the bank, and the address provided on inputs a 0-12 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba 0 , ba 1 inputs selects the bank, and the address provided on inputs a 0-8 selects the starting column location. the value on input a 10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the d/qs is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data register function table inputs output q reset# rck rck# input h hh h ll h l or h l or h x q 0 l x, or ? oating x, or ? oating x, or ? oating l truth table C commands (note 1) name (function) cs# ras# cas# we# addr deselect (nop) (9) h x x x x no operation (nop) (9) l h h h x active (select bank and activate row) (3) l l h h bank/row read (select bank and column, and start read burst) (4) l h l h bank/col write (select bank and column, and start write burst) (4) l h l l bank/col burst terminate (8) l h h l x precharge (deactivate row in bank or banks) ( 5) l l h l code auto refresh or self refresh (enter self refresh mode) (6, 7) l l l h x load mode register (2) l l l l op-code truth table C dm operation name (function) dm dqs write enable (10) l valid write inhibit (10) h x
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a speci? ed time (t rp ) after the precharge command is issued. except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. this is accomplished by using a 10 to enable auto precharge in conjunction with a speci? c read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. the device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. t his earliest valid stage is determined as if an explicit precharge command was issued at the earliest possible time, without violating t ras (min).the user must not issue another command to the same bank until the precharge time (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, without violating t ras (min). burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated. the open page which the read burst was terminated from remains open. auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits dont care during an auto refresh command. each ddr sdram requires auto refresh cycles at an average interval of 7.8125 s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some ? exibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to any given ddr sdram, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 x 7.8125 s (70.3 s). this maximum absolute interval is to allow future support for dll updates internal to the ddr sdram to be restricted to auto refresh cycles, without allowing excessive drift in t ac between updates. although not a jedec requirement, to provide for future functionality features, cke must be active (high) during the auto refresh period. the auto refresh period begins when the auto refresh command is registered and ends t rfc later.
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 register electrical characteristics parameter test conditions v cc and v ccq min typ max unit i i all inputs v i = v cc or gnd 2.7v -5 +5 a i cc static standby reset# = gnd 2.7v 10 a static operating reset# = v cc , v i = v ih (ac) or v il (ac) i o = 0 112 ma i ccd dynamic operating C clock only reset# = v cc , v i = v ih (ac) or v il (ac), ck and ck# switching 50% duty cycle i o = 0 2.5v 56 a/ mhz dynamic operating C per each data input reset# = v cc , v i = v ih (ac) or v il (ac). ck and ck# switching 50% duty cycle. all data input switching at one-half clock frequency, 50% duty cycle 180 a/clock mhz note: all typical values are at v cc = 2.5v, t a = 25c. note: stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a s tress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci? cation is n ot implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. self refresh* the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except cke are dont care during self refresh. the procedure for exiting self refresh requires a sequence of commands. first, ck must be stable prior to cke going back high. once cke is high, the ddr sdram must have nop commands issued for t xsnr , because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other command. * self refresh available in commercial and industrial temperatures only. register recommended operating conditions parameter/condition min max unit v ih ac high-level input voltage data inputs v ref +310mv v v il ac low-level input voltage data inputs v ref -310mv v v ih high-level input voltage reset# 1.7 v v il low-level input voltage reset# 0.7 v note: the reset# input of the device must be held at a valid logic level (not ? oating) to ensure proper device operation. absolute maximum ratings parameter unit voltage on v cc , v ccq supply relative to vss -1 to 3.6 v voltage on i/o pins relative to v ss -1 to 3.6 v operating temperature t a (mil) -55 to +125 c operating temperature t a (ind) -40 to +85 c storage temperature, plastic -55 to +125 c capacitance (note 13) parameter symbol max unit input capacitance: ck/ck# c i1 8 pf addresses, ba0-1 input capacitance c a 10 pf input capacitance: all other input-only pins c i2 9 pf input/output capacitance: i/os c io 10 pf bga thermal resistance description symbol max units notes junction to ambient (no air? ow) theta ja 14.2 c/w 1 junction to ball theta jb 10.8 c/w 1 junction to case (top) theta jc 4.1 c/w 1 note 1: refer to an #0001 at www.whiteedc.com in the application notes section for modeling conditions.
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 ddr dc electrical characteristics and operating conditions (notes 1, 6) v cc = +2.5v 0.2v; -55c t a +125c parameter/condition symbol min max units supply voltage v cc 2.3 2.7 v i/o supply voltage v ccq 2.3 2.7 v input hight voltage: logic 1; all inputs (21) v ih v ref + 0.15 v cc + 0.3 v input low voltage: logic 0; all inputs (21) v il -0.4 v ref - 0.15 v input leakage current: any input 0v v in v cc (all other pins not under test = 0v) i i -2 2 a output leakage current: i/os are disabled; 0v v out v cc i oz -5 5 a output levels: full drive option - x16 high current (v out = v ccq - 0.373v, minimum v ref , minimum v tt ) low current (v out = 0.373v, maximum v ref , maximum v tt ) i oh -16.8 C ma i ol 16.8 C ma output levels: reduced drive option - 16 only high current (v out = v ccq - 0.763v, minimum v ref , minimum v tt ) low current (v out = 0.763v, maximum v ref , maximum v tt ) i ohr -9 C ma i olr 9Cma i/o reference voltage v ref 0.49 x v ccq 0.51 x v ccq v i/o termination voltage v tt v ref - 0.04 v ref + 0.04 v ddr i cc specifications and conditions (notes 1-5, 10, 12, 14, 54) v cc = +2.5v 0.2v; -55c t a +125c parameter/condition symbol max 250mbps 266mbps 200mbps units operating current: one bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles; (22, 48) i cc0 625 600 ma operating current: one bank; active-read-precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle (22, 48) i cc1 850 775 ma precharge power-down standby current: all banks idle; power-down mode; t ck = t ck (min); cke = low; (23, 32, 50) i cc2p 20 20 ma idle standby current: cs# = high; all banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm (51) i cc2f 225 225 ma active power-down standby current: one bank active; power-down mode; t ck = t ck (min); cke = low (23, 32, 50) i cc3p 150 150 ma active standby current: cs# = high; cke = high; one bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle (22) i cc3n 250 250 ma operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma (22, 48) i cc4r 925 925 ma operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle (22) i cc4w 800 800 ma auto refresh current t ref = t rc (min) (27, 50) i cc5 1225 1225 ma t ref = 7.8125s (27, 50) i cc5a 30 30 ma self refresh current: cke 0.2v standard (11) i cc6 20 20 ma operating current: four bank interleaving reads (bl=4) with auto precharge, t rc =t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands. (22, 49) i cc7 2000 2000 ma
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 electrical characteristics and recommended ac operating characteristics (notes 1-5, 14-17, 33) parameter symbol 266mbps cl2.5 200mbps cl2 250mbps cl2.5 200mbps cl2 200mbps cl2.5 150mbps cl2 units min max min max min max access window of dqs from clk/clk# t ac -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns clk high-level width (30) t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clk low-level width (30) t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock cycle time cl = 2.5 (45, 52) t ck (2.5) 8 13 9 13 10 13 ns cl = 2 (45, 52) t ck (2) 10 13 10 13 13 15 ns dq and dm input hold time relative to dqs (26, 31) t dh 0.5 0.5 0.5 ns dq and dm input setup time relative to dqs (26, 31) t ds 0.5 0.5 0.5 ns dq and dm input pulse width (for each input) (31) t dipw 1.75 1.75 1.75 ns access window of dqs from clk/clk# t dqsck -0.75 +0.75 -0.8 +0.8 -0.8 +0.8 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access (25, 26) t dqsq 0.5 0.5 0.5 ns write command to ? rst dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to clk rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from clk rising - hold time t dsh 0.2 0.2 0.2 t ck half clock period (34) t hp t ch , t cl t ch , t cl t ch , t cl ns data-out high-impedance window from clk/clk# (18, 42) t hz +0.75 +0.75 +0.75 ns data-out low-impedance window from clk/clk# (18, 43) t lz -0.75 -0.75 -0.75 ns address and control input hold time (fast slew rate) (14) t ih f 0.90 0.90 0.90 ns address and control input setup time (fast slew rate) (14) t is f 0.90 0.90 0.90 ns address and control input hold time (slow slew rate) (14) t ih s 111ns address and control input setup time (slow slew rate) (14) t is s 111ns load mode register command cycle time t mrd 15 15 15 ns dq-dqs hold, dqs to ? rst dq to go non-valid, per access (25, 26) t qh t hp - t qhs t hp - t qhs t hp - t qhs ns data hold skew factor t qhs 0.75 0.75 0.75 ns active to precharge command (35) t ras 40 120,000 40 120,000 40 120,000 ns active to read with auto precharge command t rap 20 20 20 ns active to active/auto refresh command period t rc 65 65 65 ns auto refresh command period (50) t rfc 75 75 75 ns active to read or write delay t rcd 20 20 20 ns precharge command period t rp 20 20 20 ns dqs read preamble (42) t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 15 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time (20, 21) t wpres 000ns dqs write postamble (19) t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 111t ck data valid output window (25) na t qh - t dqsq t qh - t dqsq t qh - t dqsq ns refresh to refresh command interval (23) t refc 70.3 70.3 70.3 s average periodic refresh interval (23) t refi 7.8 7.8 7.8 s terminating voltage delay to v cc (53) t vtd 000ns exit self refresh to non-read command t xsnr 75 80 80 ns exit self refresh to read command t xsrd 200 200 200 t ck
13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 notes: 1. all voltages referenced to v ss . 2. tests for ac timing, i cc , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related speci? cations and device operation are guaranteed for the full voltage range speci? ed. 3. outputs measured with equivalent load: 50 ? reference point 30pf output (v out ) v tt 4. ac timing and i cc tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level speci? cations are as de? ned in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v ccq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (noncommon mode) on v ref may not exceed 2 percent of the dc value. thus, from v ccq /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref by-pass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 9. the value of v ix and v mp are expected to equal v ccq /2 of the transmitting device and must track variations in the dc level of the same. 10. i cc is dependent on output loading and cycle rates. speci? ed values are obtained with minimum cycle time with the outputs open. 11. enables on-chip refresh and address counters. 12. i cc speci? cations are tested after the device is properly initialized, and is averaged at the de? ned cycle rate. 13. this parameter is not tested but guaranteed by design. t a = 25c, f = 1 mhz 14. command/address input slew rate = 0.5v/ns. for 266 mhz with slew rates 1v/ns and faster, t is and t ih are reduced to 900ps. if the slew rate is less than 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 15. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 16. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v ccq is recognized as low. 17. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 18. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 19. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss . 22. min (t rc or t rfc ) for i cc measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i cc measurements is the largest multiple of t ck that meets the maximum absolute value for t ras . 23. the refresh period 64ms. this equates to an average refresh rate of 7.8125s. however, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 24. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 25. the valid data window is derived by achieving other speci? cations - t hp (t ck /2), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. referenced to each output group: dqs 0 with dq 0 -dq 7 ; and dqs 1 with dq 8 -dq 15 of each chip. 27. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period (t rfc [min]) else cke is low (i.e., during standby). 28. to maintain a valid level, the transitioning edge of the input must: a) sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b) reach at least the target ac level. c) after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc). 16 0 14 0 12 0 1 00 8 0 6 0 4 0 2 0 0 0 . 0 0 . 5 1. 0 1. 5 2. 0 2. 5 v out (v) i out (ma) maximum nominal high nominal low minimum figure a C pull-down characteristics figure b C pull-up characteristics 0 -2 0 -4 0 -6 0 -8 0 -1 00 -12 0 -14 0 -16 0 -18 0 -2 00 0 . 0 0 . 5 1. 0 1. 5 2. 0 2. 5 v ccq - v out (v) i out (ma) maximum nominal high nominal low minimum
14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 29. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. ck and ck# input slew rate must be 1v/ns ( 2v/ns differentially). 31. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncertain. 32. v cc must not vary more than 4% if cke is not active while any bank is active. 33. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 34. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively during bank active. 35. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis? ed prior to the internal precharge command being issued. 36. any positive glitch must be less than 1/3 of the clock and not more than +400mv or 2.9 volts, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mv or 2.2 volts, whichever is more positive. 37. normal output drive curves: a) the full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure a. b) the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure a. c) the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure b. d) the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure b. e) the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 volt, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 volt. 38. reduced output drive curves: a) the full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure c. b) the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure c. c) the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure d. d) the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure d. e) the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 v, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 v. 39. the voltage levels used are derived from a minimum v cc level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will provide signi? cantly different voltage values. 40. v ih overshoot: v ih (max) = v ccq +1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. v cc and v ccq must track each other. 42. this maximum value is derived from the referenced test load. in practice, the values obtained in a typical terminated design may re? ect up to 310ps less for t hz (max) and the last dvw. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 43. for slew rates greater than 1v/ns the (lz) transition will start about 310ps earlier. 44. during initialization, v ccq , v tt , and v ref must be equal to or less than v cc + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v cc /v ccq are 0 volts, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. 45. the current part operates below the slowest jedec operating frequency of 83 mhz. as such, future die may not re? ect this option. 46. reserved for future use. 47. reserved for future use. 48. random addressing changing 50% of data changing at every transfer. 49. random addressing changing 100% of data changing at every transfer. 50. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t rfc has been satis? ed. 51. i cc2n speci? es the dq, dqs, and dm to be driven to a valid high or low logic level. i cc2q is similar to i cc2f except i cc2q speci? es the address and control inputs to remain stable. although i cc2f , i cc2n , and i cc2q are similar, i cc2f is worst case. 52. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles before any read command. 53. all ac timings do not count extra clock needed on address and control signals to be registered. 54. ddr currents only. register currents not included. figure c C pull-down characteristics 8 0 7 0 6 0 50 4 0 30 2 0 1 0 0 0 . 0 0 . 5 1. 0 1. 5 2. 0 2. 5 v out (v) i out (ma) maximum nominal high nominal low minimum figure d C pull-up characteristics 0 . 0 0 . 5 1. 0 1. 5 2. 0 2. 5 v ccq - v out (v) i out (ma) maximum nominal high nominal low minimum 0 -1 0 -2 0 - 30 -4 0 - 50 -6 0 -7 0 -8 0
15 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 all linear dimensions are millimeters and parenthetically in inches ordering information bottom view 32.1 (1.264) max 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t r p n m l k j h g f e d c b a 25.1 (0.988) max 0.61 (0.024) nom 2.03 (0.080) max 19.05 (0.750) nom 1.27 (0.050) nom 19.05 (0.750) nom 219 x ? 0.762 (0.030) nom package dimension: 219 plastic ball grid array (pbga) white electronic designs corp. plastic ddr sdram configuration, 16m x 72 2.5v power supply registered frequency (mhz) 200 = 200mhz 225 = 225mhz 250 = 250mhz package: b = 219 plastic ball grid array (pbga) device grade: m = military -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c w 3e 16m 72 s r- xxx b x
16 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3e16m72sr-xbx february 2005 rev. 2 document title 16m x 72 registered ddr sdram multi-chip package revision history rev # history release date status rev 0 initial release august 2003 advanced rev 1 changes (pg. 1, 15, 16) 1.1 change mechanical drawing to new style november 2003 advanced rev 2 changes (pg. 1, 10, 11, 16) 2.1 change status to final 2.2 update i cc speci? cations table values 2.3 change max storage temperature to 125c 2.4 delete v ih /v il dc low-level input voltage operating condition speci? cation. 2.5 update capacitance table values february 2005 final

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